This invention relates to methods of generating test conditions for detecting delay faults in semiconductor integrated circuit including logic circuits having a plurality of signal paths, and also relates to apparatuses for generating the same. This invention also relates to apparatuses for evaluating test conditions.
After the manufacturing, semiconductor integrated circuit products should be evaluated by conducting various tests so that only the products having operable logic circuits integrated therein may be selected and shipped. Delay test for detecting delay faults is one of the various tests.
FIGS. 5A and 5B are drawings for explaining the delay test. FIG. 5A shows an exemplary logic circuit 100, and FIG. 5B is a timing chart showing exemplary operation timings in the logic circuit 100.
The exemplary logic circuit 100 shown in FIG. 5A includes a user logic 101, which is a combinational logic circuit, a start-point flip-flop 102 arranged on the input-side of the user logic 101, and an end-point flip-flop 103 arranged on the output-side of the user logic. A clock signal is supplied to clock terminals C of the flip-flops 102 and 103.
As shown in FIG. 5B, ‘H’ level data signal generated by the user-logic in the preceding stage (not shown) is supplied to D input terminal of the start-point flip-flop 102. The start-point flip-flop 102 captures the ‘H’ level data signal at the timing of a rising-edge of the clock signal. Further, after a specified delay time d1, the start-point flip-flop 102 outputs the captured data as ‘H’ level data signal from its output terminal Q. The output ‘H’ level data signal is input to the user logic 101.
After a specified delay time d2, the user logic 101 outputs a data signal, which is a ‘H’ level data signal in the example shown in FIG. 5B, based on the ‘H’ level input data signal. The output ‘H’ level data signal is supplied to data input terminal D of the end-point flip-flop 103.
If the timing when the ‘H’ level data signal is input to the D terminal of the end-point flip-flop 103 is faster than the next rising edge of the clock signal by a specified set-up time d3min, the ‘H’ level data signal is captured in the end-point flip-flop 103 at the timing of the next rising edge of the clock signal. Further, after a specified delay time d4, the acquired data signal is output from the output terminal Q as a ‘H’ level data signal and supplied to a user logic in the next stage (not shown).
The user logic 101 should be designed to output the output data signal within a delay time less than a cycle time of the clock signal or, more accurately, less than the cycle time of the clock signal by the delay times d1+d3min, which are necessary for operations of the flip-flops 102 and 103. That is, the delay time of a logic signal that passes through the user logic 101 should be designed such that the total delay time of the data path from the start-point flip-flop 101 to the end-point flip-flop 103 (d1+d2+d3min) is less than the cycle time of the clock signal.
When the user logic does not have a fatal defect, such as a defect that a transistor constituting the user logic does not operate, or a defect that a wiring between the transistors is disconnected or short-circuited, the user logic generates an output logic signal having a logical value equal to a value expected from logical values of input logic signals. Even in that situation, however, there are cases that the user logic cannot generate the output logic signal within a specified delay time (or a designed delay time) because, for example, a delay time of a transistor is larger than a designed value and/or a resistance of a wiring between transistors is higher than a designed value.
A delay test is conducted to detect such defects. In the exemplary logic circuit 100 shown in FIG. 5A, a delay test is conducted by i) setting a cycle time of the clock signal to a specified value, and ii) examining whether or not a logic signal is correctly transmitted from the preceding flip-flop (start-point flip-flop) 102 to the succeeding flip-flop (end-point flip-flop) 103.
Specifically, a delay test conducted by operating the logic circuit at “system timing”, or timing that a user actually operates the semiconductor integrated circuit (chip), is called “at-speed test”. In order to conduct the at-speed test, it is proposed to provide a clock generating circuit that generates a clock signal having edges with an interval of the system timing from a low-frequency clock signal that can be input from a tester. See, for example, “Low cost delay testing of nanometer SoCs using on-chip clocking and test compression,” Asian Test Symposium, December 2005, p. 156-161 (non-Patent document 1), which is hereby incorporated by reference in its entirety.
In practice, a user-logic is connected between respective pluralities of start-side flip-flops (start-point flip-flops) and end-side flip-flops (end-point flip-flops). The user-logic generates output signals (output data) based on input signals (input data) supplied from the plurality of start-point flip-flops. The end-point flip-flops capture and hold the generated output data at the timing of an edge of the clock signal.
Paragraphs [0045] to [0048] of US Patent Publication No. 2006-0001434 (Patent document 1), which is hereby incorporated by reference in its entirety, describe a procedure for conducting the delay test. That is, in a shift-mode (or a scan-mode), the flip-flops are connected to form a chain and a clock signal is supplied to set specified data (a test pattern) in the start-point flip-flop. Then, in the capture mode, the user logic is connected between the plurality of start-point flip-flops and plurality of end-point flip-flops and a clock signal is supplied to the flip-flops to capture output data generated by the user logic in the end-point flip-flops. Thereafter, again in the scan mode, a clock signal is supplied to the flip-flops to output the data captured and held in the end-point flip-flops from the semiconductor integrated circuit. The data output from the semiconductor integrated circuit is compared with expected values.
Specially, Patent Document 1 discloses an example of LoS (Launch-off-Shift) method. That is, i) the last clock edge of a clock signal supplied during the shift-mode is utilized as a launching clock edge for supplying the input data, which is set in the start-point flip-flops, to the combinational logic circuit, and ii) after switched to the capture mode, the next clock edge of the clock signal is utilized as a capturing clock-edge for capturing the data output from the combinational logic circuit in the end-side flip-flops. On the other hand, non-patent document 1 discloses an example of LoC (Launch-off-Capture) method. That is, after switched to the capture mode, a clock signal having a launching clock edge and a capturing clock-edge is supplied.
Further, in order to detect a small (short) delay fault that cannot be detected by the at-speed test, “faster-than-at-speed test” is also proposed. See, for example, “Kawasaki Micro maximizes delay test coverage with latest Cadence technology, Encounter True-Time now delivers faster-than-at-speed delay test for bridges and through RAMs” Cadence Design Systems, Inc., San Jose, Calif., Nov. 7, 2005 (non-Patent document 2), which is hereby incorporated by reference in its entirety. That is, a logic circuit is operated at timing faster than the system timing and examined whether or not it generates output data having a logical value equal to an expected value. Also in this case, the clock generating circuit described above may be utilized to generate a clock signal that operates the logic circuit at timing faster than the system timing.
Generally, ATPG (Automatic Test Pattern Generator) is utilized to test semiconductor integrated circuits. The ATPG automatically generates test patterns for conducting various tests on semiconductor integrated circuits. The ATPG is provided with different fault models for detecting different types of faults. Here, a fault model for detecting delay faults due to delays of signal transmissions between flip-flops is provided. The ATPG generates, based on the provide fault model, test patterns that activates signal path having each of the delay faults specified in the model.
Each of the generated test patterns includes a transition of a logical value of input data supplied to a start-side flip-flop, which constitutes a start-point of a signal path having a fault. The transition of logical value included in the test pattern is expected to propagate the signal path, or to cause transitions of logical states at nodes along the signal paths, and is further expected to cause a transition of a logical value of output data supplied to an end-point flip-flop.
FIG. 6 is a schematic drawing showing a plurality of paths that include an end-point flip-flop 203 as a common end-point. FIG. 6 shows a plurality of start-points 202 including start-side flip-flops 201_1, 202_2, 202_3, and 202_4, an end-side flip-flop 203, and a plurality of paths between them. The paths start from respective start-point flip-flops to the end-point flip-flop 203 through respective different portions 202_1, 201_2, 202_3, and 202_4 in the user logic and further through the common portion 201_5 of the user logic.
As explained above, a logic circuit provided in a semiconductor integrated circuit includes a plurality of paths having a common end-point flip-flop. One of these paths is activated when testing the semiconductor integrated circuit. For example, when a path having the start-side flip-flop 201_1 as a start-point is activated, a test pattern including a transition of logical value of input data supplied to the start-side flip-flop 201_1, by which a transition of logical value of output data supplied to the end-side flip-flop 203 is expected, is supplied to the plurality of start-points 202. By using such a test pattern, a delay fault that exists at an arbitrary position on the path from the start-point flip-flop 202_1 to the end-point flip-flop 203 through the portions 201_1 and 201_5 of the user logic may be detected.
Similarly, when a path having the start-side flip-flop 202_2 as a start-point is activated, a delay fault exists at an arbitrary position on the path from the start-point flip-flop 202_2 to the end-point flip-flop 203 through the portions 201_2 and 201_5 of the user logic may be detected. The situation is the same when a path having the start-side flip-flop 202_3 or 202_4 as a start-point is activated.
Delay faults in a logic circuit have various sizes. Here, “size of a delay fault” means an increase of delay time, from the designed value, of a path due to an existence of the delay fault on the path. When a test is conducted with a certain test timing, delay faults having a size larger than a difference between the test timing and the delay time (a designed value, i.e., a value when no delay fault exists) of the path activated by ATPG can be detected. Here, different paths have different delay times. Accordingly, a detectable size of delay fault depends on which of the paths is activated even when the test is conducted with the same test timing.
Now, “minimum slack margin” and “minimum detectable size of delay fault,” which are important factors in detecting delay faults, will be explained.
In general, when a delay fault that exists at a certain position in a logic circuit can be detected by activating any one of a group of signal paths, a difference between a delay time (a designed value with no delay fault) of the longest one of the group of paths and the system timing is called “minimum slack margin”.
For example, it may be assumed that i) a group of signal paths includes a common end-point and that ii) a delay fault exists at a portion commonly included in the group of signal paths, as shown in FIG. 6. In this case, the delay fault may be detected by activating any one of the group of paths. FIG. 6 shows a delay fault 201_5a positioned at the portion 201_5 of the user logic, which is commonly included in all of the paths, as a representative of delay faults that may be detected by activating any one of the four paths.
Accordingly, “minimum slack margin” is a difference between the delay time of the longest path among the four paths shown in FIG. 6 and the system timing. Note that, even if a delay fault exists, the delay fault does not cause a malfunction of the logic circuit at the system timing, if the size of the delay fault is smaller than the minimum slack margin.
In FIG. 6, a delay fault 201_5a is shown as a representative of delay faults that may be detected by activating any one of the four paths. Even if the delay fault 201_5a exists at any positions, other than the position shown in FIG. 6, along the four signal paths, the delay fault does not cause a malfunction of the portion of user logic shown in FIG. 6 at the system timing, if the size of the delay fault is smaller than the minimum slack margin.
On the other hand, a difference between a delay time of a path and the system timing is a size of delay fault that is detectable when ATPG activates that path. And the difference between a delay time of the longest one of the activated paths and the system timing is “minimum detectable size of delay fault”.
FIG. 7 is a schematic drawing showing an exemplary construction of a circuitry included in a chip of a semiconductor integrated circuit.
FIG. 7 shows a user logic (a combinational logic) 210, a plurality of start-points 220, and a plurality of end-points 230, which constitute an exemplary logic circuit included in an exemplary semiconductor integrated circuit. The plurality of start-points 220 includes start-side flip-flops 220_1, 220_2, . . . 220—n−1, and 220—n. The plurality of end-points 230 includes end-side flip-flops 230_1, 230_2, . . . 230—m−1, and 230—m. The user logic 210 includes a plurality of signal paths having respective different delay times.
That is, a logic circuit of a semiconductor integrated circuit includes a plurality of signal paths having respective different delay times. Accordingly, the plurality of end-point flip-flops has respective different minimum slack margins and minimum detectable sizes of delay faults.
FIG. 8 is a schematic drawing showing an exemplary relationship between the minimum slack margin and the minimum detectable size of delay fault.
FIG. 8 shows system timing and test timing, which is slower than the system timing. As explained above, even if a delay fault exists, it does not cause any influence on an actual operation of a logic circuit at the system timing, if the size of delay fault is smaller than “minimum slack margin A”, or a difference between “system timing” and “longest path”. For example, in the case shown in FIG. 6, “longest path” is the delay time of the longest one of the paths having the common endpoint 203. Accordingly, it is not necessary to detect such small delay faults, as indicated as “redundant” in FIG. 8.
On the other hand, delay faults having sizes larger than “minimum detectable size of delay fault B”, which is the difference between “longest activated path” and “test timing”, may be detected (“detectable range C”) by the delay test. For example, in the case shown in FIG. 6, “longest activated path” is the delay time of the longest one of activated paths among the paths having the common endpoint 203.
However, delay faults having sizes larger than “minimum slack margin A” and smaller than “minimum detectable size of delay default B” cannot be detected (“undetectable range D” shown in FIG. 8) even though such delay faults cause influences on the actual operation at the system timing. Accordingly, the test quality is insufficient.
As explained above, “faster-than-at-speed test” is proposed to detect such small delay faults. Previously, however, the test industry was not eager to detect small delay faults by utilizing the faster-than-at-speed test because of a risk of “overkill” or an excessive detection of small delay faults.